“The tempo at which AI has permeated nearly each side of society has been nothing wanting mind-blowing,” says CEO Van den hove, including that it’s far much less predictable than transistor scaling.
“Let’s take massive language fashions (LLMs) for example,” he provides, “whereas they may nonetheless play a task in enabling future AI breakthroughs, they arrive with a big limitation: they don’t actually study – they’re educated. I imagine the following generations of AI – agentic AI, bodily AI, and others – can be pushed by machine studying approaches equivalent to reinforcement studying, continuous studying, and autotelic studying.”
“These studying approaches will allow AI methods to construct inside world fashions – quite than depend on pre-trained language fashions – and to adapt to new conditions with out forgetting what they’ve already mastered, very like people do.”
Integrating such capabilities into AI methods will inevitably reshape the underlying chip architectures, even when the precise implications usually are not but totally understood.
“It’s why we’ve got established imec.AI-labs: a group that may join rising AI paradigms with our deep semiconductor know-how,” says Van den hove, “constructing this lean, extremely agile group of some dozen specialists – able to shifting quick and delivering significant impression – can be a significant precedence subsequent 12 months. It will likely be important to cement imec as a number one power shaping AI’s long-term roadmap, and by extension, the {hardware} roadmap for sustainable compute methods.”
Advancing the underlying chip architectures stays a high Imec precedence for 2026. This ambition drives not solely improvements in supplies and (course of) applied sciences, but in addition the continued refinement of traditional DTCO (design-technology co-optimization) and STCO (system-technology co-optimization) approaches, alongside the introduction of imec’s new cross-technology co-optimization (XTCO) paradigm.
“A brand new period of grand chip scaling challenges has begun. XTCO is our reply to these challenges,” says CEO-elect Patrick Vandenameele, “next-generation AI methods have gotten more and more advanced. To satisfy their demanding reminiscence, energy, thermal, and reliability necessities, chips are evolving into heterogeneous assemblies of a number of applied sciences that constantly work together with – and affect – each other.”
“The factor is: inside this heterogeneity lies an infinite alternative to optimise and scale throughout applied sciences. That’s the essence of XTCO. It tackles the challenges that maintain our system and fabless companions awake at night time by introducing a disruptive, holistic method to scaling – from compute density, reminiscence capability and bandwidth, and energy supply and administration, to thermal efficiency, and reliability. We imagine significant progress can solely be achieved by collectively optimizing these dimensions.”
However doesn’t fixing a bottleneck in a single space threat shifting the limitation elsewhere?
“Completely,” Vandenameele acknowledges. “That’s exactly why cross-technology scaling requires fixed iteration and dialogue throughout domains. It’s additionally why imec is uniquely positioned to steer this effort: our ecosystem brings collectively all related gamers – enabling the continual, end-to-end collaboration important for XTCO to succeed.”
“However make no mistake: supplies and (course of) know-how improvements, from introducing CFET gadgets architectures to taking the following steps within the CMOS2.0 roadmap – and bringing these improvements from lab to fab – will stay basic. That is the place enablers equivalent to Excessive NA EUV, 3D integration know-how, and photonics come into play.”
Excessive NA EUV lithography – the following main leap in patterning, enabling sub-2nm chip fabrication – was developed at document tempo within the joint ASML-imec Excessive NA EUV Lithography Lab in Veldhoven, the Netherlands.
“Constructing belief in – and de-risking – new applied sciences is the place imec has all the time performed a important function. Working intently with our companions, our mission is to mitigate dangers and guarantee a easy path to adoption. That’s exactly what we’ve got been doing on the Veldhoven lab,” saysVan den hove.
“Established to speed up Excessive NA EUV’s industrial readiness, the lab has delivered in depth information and key breakthroughs – not simply in single publicity, but in addition in patterning superior logic and DRAM constructions – demonstrating that the know-how can totally help A10 nodes.”
“From an infrastructure standpoint, 2026 is shaping as much as be an thrilling 12 months for imec, with the next-generation Excessive NA EUV scanner set to be put in on our Leuven campus,” says Van den hove, “securing this scanner – together with a full suite of state-of-the-art ASML instruments – and constructing the underlying experience in Europe is a significant achievement.”
Imec is “residence to the world’s largest patterning ecosystem, with greater than 60 companions,”’says Van den hove, “everybody who issues in lithography and patterning is right here.”
“On the analysis aspect, our focus stays on serving to prospects unlock the total potential of Excessive NA EUV – by integrating and testing it in industrial course of flows and making certain platform stability underneath actual manufacturing situations.”
“ On the identical time, we are going to proceed to push the boundaries of Excessive NA EUV by exploring next-generation nodes – together with logic A7 and A5, in addition to DRAM 0a and DRAM 0b know-how.”
“By enabling ultrafast information trade over short-reach 
and short-haul interconnects, photonics will kind the spine of large-scale, energy-efficient computing methods – important for cloud computing and superior AI workloads.”
Photonics is rising as one other cornerstone know-how – notably in the case of enabling next-generation computing.
By enabling ultrafast information trade over short-reach and short-haul interconnects, it’ll kind the spine of large-scale, energy-efficient computing methods.
That is important for cloud computing and superior AI workloads, which generate huge information flows and demand ultra-high-speed, low-power optical hyperlinks – each inside and between information centres.
“Our ambition is to evolve from being primarily an incubator to turning into a real enterprise accelerator,” says Vandenameele, “on the one hand, this implies taking imec-born ventures to the next stage of maturity – making certain they’re totally investment-ready and extremely engaging to exterior traders.”
“On the identical time, it requires deeper engagement with the worldwide enterprise capital group, enabling us to deliver the following technology of breakthrough applied sciences – whether or not originating from imec or sourced externally – efficiently to market,” provides Vandenameele.
“Democratizing entry to cutting-edge semiconductor innovation is one other highly effective approach to create impression,” continues Vandenameele, “by internet hosting the EU Chips Act’s NanoIC pilot line, as an example, we can provide trade companions early entry to beyond-2nm know-how by way of a collection of superior instruments – equivalent to early-stage course of design kits (PDKs), design-pathfinding PDKs for next-generation chip architectures, and (3D) system-exploration PDKs that help prototyping of recent elements on commercially out there foundry wafers.”
“And eventually, the transformation and growth of our IC-Hyperlink actions match completely into this technique as nicely. By broadening IC-Hyperlink’s ASIC experience, productising analysis IP, and lengthening the group’s attain into beyond-CMOS domains – consider our built-in silicon photonics (iSiPP) platform – we goal to make IC-Hyperlink a robust bridge between world-class analysis and market-ready options,” concludes Vandenameele, “the purpose: to unlock new alternatives for collaboration with fabless and system corporations, in addition to rising gamers and startups.”
