Silicon wafer sizes aren’t what you assume, and people impossibly small “3nm” and “2nm” chips you retain listening to about? They’re extra advertising and marketing label than measurement.
The newest predictions by the Interuniversity Microelectronics Centre (IMEC), not too long ago damaged down by YouTuber TechTechPotato, presents the present timeline for TSMC’s 2nm chipsets, in addition to Intel Foundry’s 18A and 14A course of applied sciences, with A14 (1.4nm) chips anticipated in 2027 and A10 (1nm) course of nodes anticipated in 2029. IMEC’s predictions even spotlight the potential of producing 0.2mm silicon as early as 2039.
In actuality, these numbers differ wildly from the bodily, measurable transistors on a chip, and we may have to attend till the late 2030s earlier than we even handle to interrupt the 10nm barrier. Here is why.
Silicon wafers aren’t as small because the 2nm dimension would make you assume
The present 2-nanometer and 1.8nm silicon applied sciences in growth by TSMC and Intel aren’t made on wafers which are 2nm in thickness.
2nm can also be not the space between two transistors on the wafer.
Chip producers are likely to consult with silicon wafers based mostly on the minimal characteristic dimension achievable on the wafer floor throughout fabrication. Proper now, that dimension often refers back to the title of the method node reasonably than any bodily characteristic of the chip.
In truth, since about 1997, silicon course of node names have been inaccurate. Intel’s 250nm course of node really had a gate size of 200nm. Intel continued this course of understatement till 2011, when silicon course of nodes dropped to 22nm, with an precise gate size of 26nm.
TSMC and Samsung additionally adopted the “notion advertising and marketing” for silicon in 2018 with the 7nm course of nodes, which have been comparable in gate size to Intel’s 10nm silicon.
And the confusion has solely continued to spiral from there.
Nevertheless, in the event you’re searching for a tough bodily measurement dimension for the present 3-nanometer chips, they’ve a gate size of 16-18nm and a steel pitch of about 23nm.
So, whatever the present 2nm and 3nm discuss, we probably will not see “true” 10-nanometer silicon till IMEC’s predicted sub-A2 chipset era in 2039.
Wafer dimension and Moore’s Legislation go hand-in-hand
As a fast refresher, Moore’s Legislation is an statement in microchip design, positing that the variety of transistors on an built-in circuit doubles roughly each two years. As silicon wafers get smaller, so do transistors, however ultimately all issues should bow to the legal guidelines of physics.
Opposite to its title, Moore’s Legislation is not an precise Legislation, however reasonably an statement in microchip design. Finally, semiconductors can solely get so small earlier than circuit warmth turns into an actual design concern.
Nvidia’s CEO, Jensen Huang, has been towards the thought of continuous the Moore’s Legislation development largely because of the increased thermal constraints of discrete graphics playing cards, whereas CPUs like Intel’s Lunar Lake chipset have extra room to develop (or shrink, on this case).
However with this reminder from IMEC concerning the true dimension of silicon wafers, and the anticipated enchancment in chip interconnect structure and transistor expertise, Moore’s Legislation appears removed from unrealistic. Whether or not the development will proceed previous the subsequent decade, we will not say for positive, nevertheless it appears to be like achievable based mostly on present projections.
That mentioned, the potential variety of transistors on these sub-A2 (10nm Lg) chipsets is staggering. The present Intel Core Extremely 9 285K has about 18 billion transistors, that means the sub-A2 chipsets might have round 300 billion transistors in 2039.
