AMD “Zen 6” Processor Households to Use a Mixture of TSMC N2 and N3 Nodes

AMD’s upcoming Zen 6 CPU household will leverage a mixture of TSMC’s N3 and N2 course of nodes, in keeping with slide decks shared with engineers at three main motherboard distributors. These paperwork define 5 distinct silicon strains set to reach in late 2026 throughout servers, desktops, and notebooks. On the server entrance, the EPYC “Venice” lineup splits into Venice basic for common‑function deployments and Venice dense for prime‑density cloud racks. Each variants use TSMC’s customized‑tuned N2P course of, providing an 8-10% clock‑pace enhance over at this time’s N3E. On the similar time, every basic die grows to 12 Zen 6 cores, and every dense die homes 32 Zen 6c cores, enabling as much as 256‑core, 512-threaded dense packages when eight dies are interconnected through the prevailing natural interposer.

For consumer programs, AMD has adopted codenames that trace at their supposed utilization profiles. “Olympic Ridge” will drive the Ryzen 10000 desktop sequence on the N2P node, whereas “Gator Vary” targets gaming laptops exceeding 55 W. The mainstream skinny‑and‑mild phase can be served by “Medusa Level,” that includes a hybrid design that pairs an N2P compute tile with an N3P I/O tile, with entry‑degree fashions choosing a value‑environment friendly monolithic N3P die. A extra detailed “Medusa Halo” and the finances‑oriented “Bumblebee” sequence are additionally within the roadmap, although their course of assignments stay below evaluation. AMD and TSMC’s shut co‑optimization of steel layers and libraries means the ultimate silicon intently resembles an “N2‑AMD” stack slightly than an ordinary N2P node. First silicon is predicted again from the fab earlier than Christmas, with quantity ramps timed for the again‑to‑faculty 2026 pocket book cycle and a subsequent server refresh wave.