{"id":9734,"date":"2025-06-25T21:16:10","date_gmt":"2025-06-25T12:16:10","guid":{"rendered":"https:\/\/aireviewirush.com\/?p=9734"},"modified":"2025-06-25T21:16:10","modified_gmt":"2025-06-25T12:16:10","slug":"two-software-program-instruments-goal-environment-friendly-design-of-two-5d-and-3d-ics","status":"publish","type":"post","link":"https:\/\/aireviewirush.com\/?p=9734","title":{"rendered":"Two software program instruments goal environment friendly design of two.5D and 3D ICs"},"content":{"rendered":"<p> <br \/>\n<\/p>\n<div>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-medium wp-image-874716\" src=\"https:\/\/static.electronicsweekly.com\/wp-content\/uploads\/2025\/06\/24195412\/Siemens-3dic-ver1-heatmap-lg-2683x2592-1-300x290.webp\" alt=\"Siemens 3D Thermal management\" width=\"300\" height=\"290\" srcset=\"https:\/\/static.electronicsweekly.com\/wp-content\/uploads\/2025\/06\/24195412\/Siemens-3dic-ver1-heatmap-lg-2683x2592-1-300x290.webp 300w, https:\/\/static.electronicsweekly.com\/wp-content\/uploads\/2025\/06\/24195412\/Siemens-3dic-ver1-heatmap-lg-2683x2592-1-1024x989.webp 1024w, https:\/\/static.electronicsweekly.com\/wp-content\/uploads\/2025\/06\/24195412\/Siemens-3dic-ver1-heatmap-lg-2683x2592-1-768x742.webp 768w, https:\/\/static.electronicsweekly.com\/wp-content\/uploads\/2025\/06\/24195412\/Siemens-3dic-ver1-heatmap-lg-2683x2592-1-1536x1484.webp 1536w, https:\/\/static.electronicsweekly.com\/wp-content\/uploads\/2025\/06\/24195412\/Siemens-3dic-ver1-heatmap-lg-2683x2592-1-2048x1979.webp 2048w\" sizes=\"auto, (max-width: 300px) 100vw, 300px\"\/><\/p>\n<p><a rel=\"image noopener\" href=\"http:\/\/www.siemens.com\/software\" target=\"_blank\">Siemens Digital Industries Software program<\/a> introduced the duo at DAC 2025. The <a rel=\"image noopener\" href=\"https:\/\/eda.sw.siemens.com\/en-US\/ic-packaging\/3d-ic-design\/\" target=\"_blank\">Innovator3D IC<\/a> suite advances 3D IC integration utilizing AI to execute chip design and lift productiveness, as designers more and more reintegrate chiplets into excessive efficiency substrates, stated the corporate.<\/p>\n<p>It permits IC designers to effectively writer, simulate and handle heterogeneously built-in 2.5D\/3D IC designs with a quick, predictable path for planning and heterogeneous integration, substrate\/interposer implementation, interface protocol evaluation compliance and knowledge administration of designs and design knowledge IP.<\/p>\n<p>Skilled on user-experience AI, it has multi-threading and multi-core capabilities to optimise capability and efficiency on designs in extra of 5m pins. Its Innovator3D IC Integrator is a consolidated cockpit for setting up a digital twin utilizing a unified knowledge mannequin for design planning, prototyping and predictive evaluation. It additionally contains Innovator3D IC Format for correct-by-construction package deal interposer and substrate implementation. Different parts are the Innovator3D IC Protocol Analyzer for chiplet-to-chiplet and die-to-die interface compliance evaluation and Innovator3D IC Knowledge Administration to handle designs and design knowledge IP.<\/p>\n<p><?php echo do_shortcode('[inread_parallax slot=\"DFP-EW-InRead2-Mobile\" width=\"300\"]'); ???><\/p>\n<style><![CDATA[<![CDATA[ #DFP-EW-InRead2-Mobile { display: block!important; } @media only screen and (max-width: 768px) {  } ]]]]><![CDATA[>]]><\/style>\n<p>&#13;<br \/>\n<\/p>\n<p><?php echo do_shortcode('[inread_parallax slot=\"DFP-EW-InRead2-Mobile\" width=\"300\"]'); ???><\/p>\n<style><![CDATA[<![CDATA[ #DFP-EW-InRead2-Mobile { display: block!important; } @media only screen and (max-width: 768px) {  } ]]]]><![CDATA[>]]><\/style>\n<\/p>\n<p>The second announcement is the Calibre 3DStress software program, designed to determine {the electrical} affect of stress on the transistor stage. It makes use of superior thermo-mechanical evaluation to optimise the yield, reliability and complexity (pictured).<\/p>\n<p>The problem is that 2.5D\/3D gadgets have thinner dies and better package deal processing temperatures. For that reason, the software program helps transistor-level evaluation, verification, and debugging of thermo-mechanical stresses and warpage in 3D IC packaging. Chip designers are due to this fact capable of consider chip-package interplay earlier within the growth cycle.<\/p>\n<blockquote class=\"wp-embedded-content\" data-secret=\"h6Ktx3ruwk\">\n<p><a rel=\"image noopener\" href=\"https:\/\/www.electronicsweekly.com\/news\/design\/eda-and-ip\/siemens-and-ifs-certify-tools-2025-05\/\" target=\"_blank\">Siemens and IFS certify instruments<\/a><\/p>\n<\/blockquote>\n<p><iframe loading=\"lazy\" class=\"wp-embedded-content\" sandbox=\"allow-scripts\" security=\"restricted\" style=\"position: absolute; visibility: hidden;\" title=\"\u201cSiemens and IFS certify tools\u201d \u2014 Electronics Weekly\" src=\"https:\/\/www.electronicsweekly.com\/news\/design\/eda-and-ip\/siemens-and-ifs-certify-tools-2025-05\/embed\/#?secret=QX8VdWwzY4#?secret=h6Ktx3ruwk\" data-secret=\"h6Ktx3ruwk\" width=\"600\" height=\"338\" frameborder=\"0\" marginwidth=\"0\" marginheight=\"0\" scrolling=\"no\"><\/iframe><\/p>\n<\/p><\/div>\n<p><script>\n\twindow.___gcfg = {lang: 'en-US'};\n\t(function(w, d, s) {\n\t  function go(){\n\t\tvar js, fjs = d.getElementsByTagName(s)[0], load = function(url, id) {\n\t\t  if (d.getElementById(id)) {return;}\n\t\t  js = d.createElement(s); js.src = url; js.id = id;\n\t\t  fjs.parentNode.insertBefore(js, fjs);\n\t\t};\n\t\tload('\/\/connect.facebook.net\/en\/all.js#xfbml=1', 'fbjssdk');\n\t\tload('https:\/\/apis.google.com\/js\/plusone.js', 'gplus1js');\n\t\tload('\/\/platform.twitter.com\/widgets.js', 'tweetjs');\n\t  }\n\t  if (w.addEventListener) { w.addEventListener(\"load\", go, false); }\n\t  else if (w.attachEvent) { w.attachEvent(\"onload\",go); }\n\t}(window, document, 'script'));\n\t<\/script><br \/>\n<br \/><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Siemens Digital Industries Software program introduced the duo at DAC 2025. The Innovator3D IC suite advances 3D IC integration utilizing AI to execute chip design and lift productiveness, as designers more and more reintegrate chiplets into excessive efficiency substrates, stated the corporate. It permits IC designers to effectively writer, simulate and handle heterogeneously built-in 2.5D\/3D [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":9736,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[10],"tags":[],"class_list":{"0":"post-9734","1":"post","2":"type-post","3":"status-publish","4":"format-standard","5":"has-post-thumbnail","7":"category-gadgets"},"_links":{"self":[{"href":"https:\/\/aireviewirush.com\/index.php?rest_route=\/wp\/v2\/posts\/9734","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/aireviewirush.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/aireviewirush.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/aireviewirush.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/aireviewirush.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=9734"}],"version-history":[{"count":1,"href":"https:\/\/aireviewirush.com\/index.php?rest_route=\/wp\/v2\/posts\/9734\/revisions"}],"predecessor-version":[{"id":9735,"href":"https:\/\/aireviewirush.com\/index.php?rest_route=\/wp\/v2\/posts\/9734\/revisions\/9735"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/aireviewirush.com\/index.php?rest_route=\/wp\/v2\/media\/9736"}],"wp:attachment":[{"href":"https:\/\/aireviewirush.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=9734"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/aireviewirush.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=9734"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/aireviewirush.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=9734"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}